Texas Instruments LFN Series Sample & Hold Amplifiers are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Texas. lf Sample & Hold Amplifiers are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for lf Sample & Hold Amplifiers. Understand the working of LF IC (sample-and-hold circuit). • Describe the concept of sampling a time varying signal. • Obtain the sampled and hold otuput.

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If you plot the output voltage versus time, you will find a straight line with a slope of This corresponds to a leakage current of only 33 pA, an excellent result.

It is obvious that the capacitor should have small leakage, so all electrolytics, whether aluminum or tantalum, are excluded. The switch is made from a JFET, which does very well. For the LF, with a 0. LS or HC logic will do very well. The capacitor voltage changes as the dielectric “relaxes,” as well as when charge is supplied or taken away.

The similarity to our test circuit is obvious. The control logic input is applied to a differential amplifier to allow interfacing with various logic families.

There is a settling time after the hold command until the output is within 1 mV of its steady value. Selection of the hold capacitor is an important matter. Note that we did not do much worse than this with our discrete circuit.

The leakage current is found to be 30 pA.

The circuit is basically two unity-gain buffers, with a hold capacitor between kf398, and a switch to disconnect the input. For the LF, this is about 0.


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The smaller the hold capacitor, the more quickly it can be charged and the smaller the acquisition time. The next most important characteristic is “dielectric absorption” or hysteresis in the dielectric constant.

To sample, the gate is connected to the drain or the sourceand to hold, the gate is lf389 to -V.

The LF is connected as shown at the left. In fact, if the input voltage to be digitized is varying, a sample-and-hold circuit is mandatory. This is not a very convenient way to control the JFET, but it works for a demonstration. For us, we want to refer the logic to ground by connecting pin 7 to ground, and apply a positive input to pin 8 for the sample state. Record the lff398 at the start, and at every even volt as the output voltage droops.

What happens is this: These diodes then require the 30k resistor to avoid overloading the output amplifier. Finally, there is droop as l3f98 hold capacitor voltage declines steadily in the “hold” state. This demonstrates that the droop is caused by a constant leakage current, and is not an exponential RC decay. Polypropylene has the least hysteresis of all, and is the best choice for a hold capacitor, but lg398 of the three will give adequate results.

A more practical discrete sample-and-hold circuit is given in Signal Switching. The voltage kept on decreasing, until it reached some internal saturation value at Apply an input voltage with a potentiometer, and watch the output voltage track it while lf3998 gate is connected to the drain.

The acquisition time depends on the size of the hold capacitor.

Measure the time required for it to fall by 1 V. This gain error is less than 0. We also measure the leakage currents that exist in these circuits. For a hold capacitor ,f398 0. The acquisition time is the time for the internal nodes to settle, and the output to be within, say, 0. Secondly, there is a finite jump in the output voltage called the hold step when the hold command is issued. The larger the hold capacitance, the smaller is the droop. After the hold command, the aperture time is the time after which changes of the input voltage no longer affect the output voltage.


Times from the hold command are measured from the 1.

Buffer a slow signal with an LS For most normal uses, a value of 0. When the control is changed to “hold,” below 1. One change is that the feedback loop is extended from input to output. This requires the opposed diodes that “catch” the output of the first op-amp when the feedback loop is broken in the “hold” state. lf38

For the LF, it is ns. In the test, I used my debounced pushbutton for the logic signal, choosing the normally-low output. The type of capacitor used is important. Bipolar op-amps are not suitable, because the input base currents are too large. There is, therefore, a tradeoff in selection of hold capacitor size. I found about 5 minutes, so the droop rate is 3.

The LF is, however, an excellent circuit suitable for most peaceful requirements. The specifications of the LF allow it to be up to pA. Calvert Created 29 July Last revised 30 July